wafer.space Community - Whoa. Radiation-tolerant how?

2:24 p.m.

From what I understand, this depends on the layout: you have actual tap rings around your transistors, and the nmos is an ring-shaped.

2:24 p.m.

2:25 p.m.

See here. Of course this will reduce the density of your digital design.

Oh the pmos doesn't ? Interesting, I didn't know it was nmos only.

Yeah, I would have expected the same ^^

2:26 p.m.

Tim will be able to tell us why that's the case.

I wonder how annular gates make things radiation stable

Note that this SCL targets long-term effects of radiation (TID). It does not protect against single-event upsets, as I understand it.

2

@brookieoz Something about charges getting trapped n the gate where the poly enters the diffusion IIUC.

Please make sure you run this by legal; there may be consequences (export restrictions) for rad-hard parts / technology. The EU is very sensitive on that now, not sure how things are in the US.

2:41 p.m.

See Category 3 in: https://eur-lex.europa.eu/eli/reg/2021/821/2026-09-21

Please poke me if there are legal issues with using this SCL so I can know if its okay for me to use

There is a difference between "rad-hard" and "rad-tolerant by design". "rad-hard" chips are pre-dosed with radiation, are made in special fab processes, are generally used by the military, and are definitely restricted. These cells are designed on basic well-known principles that mitigate total dose radiation effects, and they aren't even guaranteed to any specific dose because I don't have access to any of that information. After doing some simulations, it's not even clear to me that the regular standard cells would fail under moderate or even high doses of radiation. They will definitely start leaking excessive quiescent current, but maybe not enough to invalidate the logic states.